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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information Low Voltage 1:12 Clock Distribution Chip
The MPC948L is a 1:12 low voltage clock distribution chip. The device is pin and function compatible with the MPC948 with the added feature of 2.5V output capabilities. The device features the capability to select either a differential LVPECL or a LVTTL compatible input. The 12 outputs are 2.5V LVCMOS or LVTTL compatible and feature the drive strength to drive 50 series terminated transmission lines. With output-to-output skews of 350ps, the MPC948L is ideal as a clock distribution chip for the most demanding of synchronous systems.
MPC948L
LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP
* * * * * * * * *
Clock Distribution for Intel Microprocessors LVPECL or LVCMOS/LVTTL Clock Input 350ps Maximum Output-to-Output Skew Drives Up to 24 Independent Clock Lines Maximum Output Frequency of 150MHz Synchronous Output Enable Tristatable Outputs 32-Lead TQFP Packaging 2.5V Output Capability
FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-02
With an output impedance of approximately 7, in both the HIGH and LOW logic states, the output buffers of the MPC948L are ideal for driving series terminated transmission lines. More specifically, each of the 12 MPC948L outputs can drive two series terminated 50 transmission lines. With this capability, the MPC948L has an effective fanout of 1:24 in applications where each line drives a single load. The differential LVPECL inputs of the MPC948L allow the device to interface directly with a LVPECL fanout buffer like the MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the TTL_CLK_Sel pin will select the TTL level clock input. All of the control inputs are LVCMOS/LVTTL compatible. The MPC948L provides a synchronous output enable control to allow for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test, the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into high impedance. Note that all of the MPC948L inputs have internal pullup resistors. The 32-lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. The MPC948L features two independent power supplies; VCCI and VCCO. The VCCI pin powers the internal core logic and must be tied to 3.3V. The VCCO pin powers the output buffer and can be tied to either 2.5V or 3.3V.
This document contains information on a new product. Specifications and information herein are subject to change without notice. 4/97
(c) Motorola, Inc. 1997
1
REV 0
MPC948L
VCCI PECL_CLK PECL_CLK TTL_CLK TTL_CLK_Sel Sync_OE Tristate
VCCO
0 1
12
Q0-Q11
Figure 1. Logic Diagram
VCCO VCCO 18
GND
GND
Q4
Q5
Q6
24 Q3 VCCO Q2 GND Q1 VCCO Q0 GND 25 26 27 28
23
22
21
20
19
Q7 17 16 15 14 13 GND Q8 VCCO Q9 Sync_OE 12 11 10 9 GND Q10 VCCO Q11 0 1 Tristate 0 1 Outputs Disabled Enabled Outputs Tristate Enabled
FUNCTION TABLES
TTL_CLK_Sel 0 1 Input PECL_CLK TTL_CLK
MPC948L
29 30 31 32 1 2 3 4 5 6 7 8
PECL_CLK
TTL_CLK_Sel
PECL_CLK
TTL_CLK
Tristate
VCCI
Figure 2. 32-Lead Pinout (Top View)
TTL_CLK
Sync_OE
Q
Sync_OE
Figure 3. Sync_OE Timing Diagram
MOTOROLA
GND
2
TIMING SOLUTIONS BR1333 -- Rev 6
MPC948L
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 4.6 VDD + 0.3 20 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
DC CHARACTERISTICS (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 2.5V 5% or 3.3V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Maximum Quiescent Supply Current 25 22 30 PECL_CLK Other PECL_CLK Other PECL_CLK PECL_CLK VCCO = 3.3V VCCO = 2.5V Min 2.135 2.0 1.49 300 VCC - 2.0 2.5 2.0 0.4 100 4 Typ Max 2.42 3.60 1.825 0.8 1000 VCC - 0.6 Unit V V mV V V V A pF pF mA Per Output Note 1. IOH = -20mA (Note 2.) IOL = 20mA (Note 2.) Note 3. Condition Single Ended Spec Single Ended Spec
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "HIGH" input is within the VCMR range and the input swing lies within the VPP specification. 2. The MPC948L outputs can drive series or parallel terminated 50 (or 50 to VCC/2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull-up resistors which affect input current, PECL_CLK has a pull-down resistor.
AC CHARACTERISTICS (TA = 0 to 70C, VCCI = 3.3V 5%; VCCO = 2.5V 5% or 3.3V 5%)
Symbol Fmax tpd tsk(o) tsk(pr) tpwo ts th tPZL,tPZH tPLZ,tPHZ tr, tf 4. 5. 6. 7. Characteristic Maximum Input Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Output Pulse Width Setup Time Hold Time Output Enable Time Output Disable Time Output Rise/Fall Time Sync_OE to PECL_CLK Sync_OE to TTL_CLK PECL_CLK to Sync_OE TTL_CLK to Sync_OE PECL_CLK to Q TTL_CLK to Q tCYCLE/2 - 800 1.0 0.0 0.0 1.0 3 3 0.20 11 11 1.0 1.5 2.0 tCYCLE/2 + 800 PECL_CLK to Q TTL_CLK to Q Min 150 7.0 7.9 350 Typ Max Unit MHz ns ps ns ps ns ns ns ns ns 0.8V to 2.0V Condition Note 4. Note 4. Note 4. Notes 4., 5. Notes 4., 6. Measured at VCC/2 Notes 4., 7. Notes 4., 7.
Driving 50 transmission lines Part-to-part skew at a given temperature and voltage Assumes 50% input duty cycle. Setup and Hold times are relative to the falling edge of the input clock
TIMING SOLUTIONS BR1333 -- Rev 6
3
MOTOROLA
MPC948L
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC948L clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC948L clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC948L clock driver is effectively doubled due to its capability to drive multiple lines. combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
1.0
0.5
0 2 4 6 8 TIME (nS) 10 12 14
MPC948L OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA
Figure 5. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC948L OUTPUT BUFFER 7 RS = 36 ZO = 50
MPC948L OUTPUT BUFFER IN 7
RS = 43
ZO = 50 OutB0
RS = 43
ZO = 50 OutB1
RS = 36
ZO = 50
Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC948L output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC948L. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel
7 + 36 k 36 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use.
MOTOROLA
4
TIMING SOLUTIONS BR1333 -- Rev 6
MPC948L
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS BR1333 -- Rev 6
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
5
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
MPC948L
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315
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MOTOROLA
6
MPC948L/D TIMING SOLUTIONS BR1333 -- Rev 6

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